2021年1月10日 星期日

Linux Kernel(21)- Pulse-Width Modulation


Duty cycle,所謂的Duty Cycle指的是一段時間內on的百分比(The term duty cycle describes the proportion of 'on' time to the regular interval or 'period' of time),如下圖


Polarity,這裡的Polarity指的是high active或是low active,
 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
 * cycle, followed by a low signal for the remainder of the pulse
 * period
 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
 * cycle, followed by a high signal for the remainder of the pulse
 * period

PWM常被當成是信號調變(modulation)的一種形式,在一端進行編碼並在另一端進行解碼。通常我們會拿來控制LED或馬達等裝置。
          _      _      _      _      _      _      _      _     
         | |    | |    | |    | |    | |    | |    | |    | |    
Clock    | |    | |    | |    | |    | |    | |    | |    | |    
       __| |____| |____| |____| |____| |____| |____| |____| |____

                 _      __     ____          ____   _
PWM signal      | |    |  |   |    |        |    | | |
                | |    |  |   |    |        |    | | |
       _________| |____|  |___|    |________|    |_| |___________

Data       0     1       2      4      0      4     1      0
The inclusion of a clock signal is not necessary, as the leading edge of the data signal can be used as the clock if a small offset is added to each data value in order to avoid a data value with a zero length pulse.

                _      __     ___    _____   _      _____   __     _   
               | |    |  |   |   |  |     | | |    |     | |  |   | | 
PWM signal     | |    |  |   |   |  |     | | |    |     | |  |   | |  
             __| |____|  |___|   |__|     |_| |____|     |_|  |___| |_____

Data            0       1      2       4     0        4      1     0





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